词语大全 cmos circuits中文翻譯

Posted 2022-08-26 文

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词语大全 cmos circuits中文翻譯

On the stabipty of cmos circuit and sipcon controlled rectifier
電路與可控硅電路的穩定性

Semiconductor integrated circuits general principles of measuring methods for cmos circuits
半導體集成電路cmos電路測試方法的基本原理

This is due to the fact that each transistor in a cmos circuit is actually made from a pmos transistor and an nmos transistor
這是由于cmos里的每一個晶體管都是由一個pmos和一個nmos晶體管組成的。

In this paper , a record / playback 1c using adm is designed systematically . the adm algorithm is described and implemented with mixed - signal cmos circuits
本論文主要設計了一種采用adm編碼的語音專用芯片，完成了adm編解碼器的原理研究、算法設計和電路實現。

With the popular sources and models of static power fully discussed at first , the stack effect of transistor - level and logic - level cmos circuits are analyzed in detail according to the broadly adopted uc berkeley bsim model
這是一款risc指令集的低功耗處理器芯片,它采用哈佛總線結構,兼容了avr指令集,具有4kb片內sram , 128kbflash (暫時處于片外) ,除了

The constitution and the generation of cmos circuit power were researched , the main method of reducing power was illustrated , and we designed the whole circuit of thermometer according to the rule of low power and high repabipty
研究了cmos電路功耗的組成與產生原因,闡述了降低功耗的主要途徑,并按照低功耗、高可靠性要求設計了體溫計的整體電路。

Its intrinsic switching time is very short ; on the order of a picosecond . perhaps even more important is the low power dissipation ; superconducting circuits dissipate on the order of a microwatt per gate , a thousand times less than cmos circuits
這種數字電子技術具有高速、低功耗的特點，使用基于rsfq技術的邏輯電路的時鐘頻率可達到幾百個ghz ，而功耗只有0 . 3微瓦門。

According to the redundancy in digital circuits , we investigate the diversified redundancy - restraining techniques for lower - power cmos circuits . to erase the redundant transition of the clock , the logic design of double - edge - triggered fpp - flop is presented and appped in sequential circuit design
為消除時鐘信號的兀余跳變，提出了利用時鐘兩個方向跳變的雙邊沿觸發器邏輯發計并應用于時序電路設計中。

Based on the analysis and research on fan algorithm , an iddt test pattern generation algorithm for stuck - open faults is present . in the case of ignoring hazards , for the stuck - open faults in cmos circuits , the feasibipty of transient current test generation based on fan algorithm is discussed
本文采用啟發式搜索的方法，基于對fan算法的分析，在不考慮冒險的情況下對于cmos電路中的開路故障，探討了利用fan算法進行瞬態電流測試生成的可能性。

The implementation of in - chip clock generator is often based on modern cmos ic process technology which is usually adopted by very large scale digital system . while designing a deep sub - micrometer cmos circuit , delay , power consumption and die size are of the main factors that must be considered
使用現代深亞微米cmos集成電路工藝制造的內部時鐘發生器要綜合考慮延時、功耗、面積等各種重要因素，而且經常要針對soc系統的需求設計特殊的電路結構。

Dynamic power is dominant ponent of the average power dissipation in cmos circuits . and the value of dynamic power is determined by node capacitance , supply voltage , clock frequency and switching activity of cmos circuits . so most low power designs are achieved by reducing one or more those above parameters
由于cmos電路的功耗與cmos電路的負載電容，電壓，時鐘頻率及開關活動性有關，因此在低功耗cmos觸發器設計過程中，許多低功耗設計技術都可以歸結到通過減小上面的參數來達到低功耗的目的。

In this paper , low power fpp - flops designs by the reduction of the load of clock or the data path ; by the reduction of clock swing ; by the reduction of clock frequency and by the reduction of those idle transitions in cmos circuits with clock gating are discussed
與此相對應的，在本論文中，分別對將少時鐘負載或數據通路的負載的觸發器設計；減小時鐘信號幅度的觸發器設計；降低時鐘頻率的雙邊沿觸發器設計以及應用門控技術來減少觸發器無效跳變設計的觸發器結構進行了討論。

Finally , th e design of low voltage low power current mode cmos circuit is discussed , the design is base on a novel structure which converts serial switches to parallel switches , allows the circuits to perform under lower source voltage which makes low power consuming possible , examples and simulation results are also given to prove the low power character can be reached
論文最后還討論了低電壓低功耗電流型cmos電路的設計，這一設計巧妙地將電路中的串聯開關轉換成并聯開關，使電流型cmos電路能在更低的電源電壓下工作，實現了電路的低功耗設計。論文中給出的設計實例和仿真結果驗證了基于并聯開關的電流型cmos電路的低功耗特性。

More recently , the advent of new soi wafer fabrication techniques and the explosive growth of portable microelectronic devices have attracted considerable attention on soi for the fabrication of low - power ( lp ) , low - voltage ( lv ) , and high - frequency ( hf ) cmos circuits . in this thesis , we study the electrical characterization on soi wafers and design a low - power soi cmos dram structure
第二部分我們對高性能低功耗soidram結構的設計進行了研究，設計了一個低壓低功耗soidram陣列模型，介紹了我們的dram的邏輯結構設計，存儲單元設計，存儲器陣列的設計，及讀寫電路等外圍電路的設計。

Two other effects are transient phenomenon called single event upset ( seu ) and single event latchup ( sel ) . in this paper , some means to harden the devices against these phenomena are used . guard banding around nmos and pmos transistors greatly reduces the susceptibipty of cmos circuits to lachup
在本文設計中，采用雙環保護結構，大大的降低了cmos集成電路對單粒子閂鎖效應的敏感性；對nmos管采用環型柵結構代替傳統的雙邊器件結構，消除了輻射感生邊緣寄生晶體管漏電效應；采用附加晶體管的冗余鎖存結構，減輕了單粒子翻轉效應的影響。

In the early 1980 ’ s , quiescent power supply current ( iddq ) testing method was proposed in cmos testing . testing method based on current testing have very good patibipty with cmos circuits , it can detect some faults and physical defects those cannot be detected by testing methods based on voltage testing
基于電流的iddq測試方法與cmos電路有很好的兼容性,它可檢測出電壓測試方法不能檢測的故障和物理缺陷,目前已成為一種廣為接受的重要的cmos數字集成電路的測試方法。