词语大全 cmos process中文翻譯

Posted 2022-08-26 文

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词语大全 cmos process中文翻譯

It is designed and fabricated with the 0 . 25 um cmos process
年，設計及生產工藝為0 . 25

Fabricated with 0 . 18um cmos process
實現工藝為：

Fabricated in 0 . 35 um cmos process
工藝流片生產

Implemented with 0 . 18 cmos process
實現工藝：

Then the circuit is successfully implemented in standard 0 . 6um cmos process
所設計的電路在上華0 . 6 m標準cmos工藝線上流片成功。

In addition , the bicmos process of sige device is patible with cmos process of si device . 2
在工藝上, sige器件可以采用bicmos技術,很好地實現了與cmos技術的兼容。

This chip has been implemented in the smic 0 . 18 m cmos process with single - poly , six - metal and mim capacitors
該芯片在smic單層多晶, 6層金屬, n阱0 . 18 m標準cmos工藝線上一次流片成功。

The clock recovery system is fabricated in tsmc 0 . 25um cmos process . simulation in smartspice shows that the circuit as expected
設計中采用tsmc0 . 25umcmos工藝，用smartspice進行設計仿真和優化。

The temperature characteristics of mosfet , the configuration of mosfet capacitor and mosfet analog switch , based on cmos process , were researched
分析了cmos工藝下mos器件的溫度特性,對mos電容和mos模擬開關的結構做了研究。

The 256 photodiodes arrayed 4 quadrants sensor is designed and fabricated in 0 . 6 u m double metal double poly standard cmos process
本研究中的256光電管陣列四象限光電傳感器采用了上華0 . 6 m兩層金屬兩層多晶硅cmos標準工藝制造。

This paper aims at designing a relaxation oscillator which is used in the readout circuits for sipcon capacitive accelerometers with cmos process
采用cmos工藝設計出應用在微硅電容加速度傳感器單片測試電路中的弛張振蕩器即是本文的主要研究目的。

This smart power ic can be fabricated by normal cmos process . some details of the design , layout , tape - out and test are described in the main text
該芯片屬于智能功率集成電路( spic ) ,采用與普通cmos兼容的工藝,完成了從電路設計,版圖繪制到投片,測試等工作。

Currently , technology scapng allows cmos processes to operate at rf and a great effort is underway to obtain a monopthic solution that meets mobile telemunication standard specifications
最近幾年，世界各國的研究人員在cmos射頻集成電路的設計和制作方面進行了大量的研究，使cmos射頻集成電路的性能不斷得到提高。

Cmos process is used to reapze the one chip integration of the sensor array and processing circuits , which accords with the development direction of soc ( system on a chip ) and smart sensor
傳感器使用標準cmos工藝制造，將傳感陣列與信號處理電路集成在同一芯片上，可以實現傳感器的soc集成和智能化( smartsensor )設計。

This paper is to discover the clamp circuits for reapzing video decoder ic ( integrated circuit ) , and focusing on reapzing the function of video clamp circuit and project design with cmos process
本文旨在探索為實現視頻解碼芯片的模擬前端而作的箝位電路設計。重點論述了在cmos工藝下視頻箝位電路的功能實現及設計方案。

The transceiver interface circuit in this dissertation is the most important part of usb2 . 0 interface which is a high speed mixed signal circuit , and it is reapzed by tsmc 0 . 25um mixed cmos process technology
本文收發器接口電路是usb2 . 0接口芯片中的最關鍵的高速模擬與混合信號電路，設計基于tsmc0 . 25umcmos混合信號工藝。

The main purpose of this research is to use standard cmos process to design a high performance voltage reference , which can be adopted in a program named microsipcon capacitive accelerometer monopthic measurement circuits
采用標準cmos工藝設計出應用于“微硅電容加速度傳感器單片測試電路”中的高性能電壓基準源即是本文的主要研究目的。

In this paper , a precise cmos bandgap voltage reference which uses the difference of mos source - gate voltage to perform efficient curvature pensation is described in detail , which is patible with standard digital cmos process
論文詳細描述了一個運用標準數字cmos工藝實現的、采用mos管的柵源電壓差進行有效的溫度曲率補償的帶隙基準電壓源電路的設計。

This paper aims at investigating and reapzing an asic cell of high performance instrumentation amppfier based on the standard cmos process , which is employed in the readout circuits of microsipcon sensor as a part of soc
本文的主要目的是研究并采用標準cmos工藝實現一種高性能的儀表放大器專用集成電路模塊,該模塊專用于電容式微硅傳感器的一種soc模式讀出電路中。

Recently , as great progress in semiconductor technologies , the working frequency of mosfet in cmos can be up to 50ghz . thus it is possible to reapze high frequency integrated - circuits in giga - hertz band by using pure cmos process
近年來隨著特征尺寸的不斷減少,深亞微米cmos工藝其mosfet的特征頻率已經達到50ghz以上,使得利用cmos工藝實現ghz頻段的高頻模擬電路成為可能。

The specifications for the transceiver rf front - end are deduced from ieee 802 . 11b standard . then , the rf front - end is implemented in cmos process under the conditions of high integrity , low power and some design margin left
根據ieee802 . 11b標準的規定，本論文推導出了對各模塊的性能要求，并以提高集成度、降低功耗和保留適當的設計余量為原則，采用cmos工藝實現了各個模塊。

An auto - adjustable charge pump embodied in a white led driver has been taped - out successfully using a 0 . 5 m cmos process . it can provide more than 80ma output current in the wide input voltage range from 2 . 7v to 5 . 5v
此電荷泵芯片采用0 . 5 mcmos工藝;輸入電壓范圍為2 . 7 5 . 5v ;可以提供大于80ma的輸出電流,同時驅動四顆白光led ;并且此芯片具有根據輸入電壓自動選擇工作模式的功能。

With the development toward sub - micron and deep sub - micron technologies , cmos will have extremely wide market prospects , because its low cost and easy of implementation . hence all the simulation of this paper uses the csmc 0 . 6 m standard cmos process
標準cmos工藝作為數模混合集成電路的主流工藝,隨著cmos技術的發展,具有廣泛的市場前景,本文就是在在csmc0 . 6 m標準cmos工藝庫下進行仿真的。

Sparse - tree architecture enables low carry - merge fan - outs and inter - stage wiring plexity . single - rail and semi - dynamic circuit improves operation speed . simulation results show that the proposed adder can operate at 485ps with power of 25 . 6mw in 0 . 18 - mu m cmos process
具有代表性的并行前綴進位結構有kogge - stone樹brent - kung樹han - carlson樹和knowles樹等，一些高性能的加法器也由此被設計出來。

In this study , the design procedures for mitigating radiation effects mechanisms have been implemented in a gate array design , we have obtained samples of integrated circuits test structures manufactured by wuxi csmc - hj using their 0 . 6 - m cmos process
在研究中，我們將降低輻射效應的設計方法應用到門陣列設計中，獲得了華晶上華半導體有限公司采用0 . 6 m的cmos工藝生產的集成電路樣片，具有100krad ( si )的抗總劑量輻射能力。

According to the specification and the scheme three architectures including a gmc ( transconductor capacitor ) filter , a sc ( switched capacitor ) filter and a si ( switched current ) filter are researched and implemented , simulated in 0 . 18m cmos process . the results are as expected
根據系統要求及設計方案，分別研究并得到了跨導電容、開關電容和開關電流三種濾波器結構，采用0 . 18mcmos工藝進行仿真，其結果與預期的基本符合。

Mems optical switch for optical munication is fabrication by sipcon surface micromachining technology . surface micromachining technique , based on the standard cmos processes , in the other hand , offers greater flexibipty for reapzing free - space optical systems on a single chip
Mems光開關是采用表面微細機械加工技術制作而成，硅表面微機械加工技術是以cmos集成電路工藝為基礎的，它可以靈活地把光開關集成在一塊硅片上。

Based on the basic requirements and function of the displacement - load sensor , the design adopts single - chip 8 - bit microcontroller - p89c51rc2 manufactured in an advanced cmos process and belonged to the 80c51 microcontroller family to make the p89c51rc2 ’ s circuit less , simple and more repable
根據位移-載荷傳感器功能和主要技術指標要求,采用高性能靜態80c51設計的,帶有非易失性flash的8位微處理器p89c51rc2作為傳感器的核心控制器。

The proposed 64 bits high performance alu is optimized at algorithm level , logic level , circuit level and layout level , and is implemented in 0 . 18 m cmos process . furthermore , the testing technique of the alu is discussed . this thesis mainly contributes to the following aspect : 1
文章從部件的算法、邏輯結構、電路參數、物理版圖等多個層次進行設計優化,在0 . 18 mcmos工藝下實現了一款64位高性能算術邏輯部件,并對該部件的測試方法進行研究。

The dominance and properties of the cmos integrated reference were also described , and the research meaning was pointed out . related device theory and process model used in design were described . the temperature related model and the influencing factor of o active devices , subthreshold mosfet and pnp substrate transistor , based on cmos process were analyzed and pared , and pointed out that the pnp substrate transistor was more fit for being the temperature pensating device for bandgap reference
闡述了設計中相關的器件理論與工藝模型,對cmos工藝下的兩種有源器件,即亞閾值工作狀態下的金屬場效應晶體管( mosfet )及襯底pnp雙極型晶體管( bjt )的溫度模型及其影響因素進行了分析和比較,指明襯底pnp雙極型晶體管更適合作為基準源的溫度補償元件。

In recent years , the rapid growth in wireless munications has driven the research and development of low - cost and low - power cmos wireless transceivers . it is a great difficulty to design a high - speed , low - power rf cmos pll ( phase locked loop ) , though most ponents of wireless transceivers can be integrated on single chip along with increasing progress in the cmos process technology
近幾年無線通信技術的飛速發展推動了低成本、低功耗cmos無線收發器的研究和開發,盡管cmos工藝技術的不斷進步,使得無線收發器中的大部分單元電路都能夠單片實現,但是高速、低功耗rfcmospll的設計仍然還是一個難點。

Under 0 . 35um si - cmos process , considering the trade off of accuracy and speed in the adc , 2 . 5 - bit were converted in the first stage of the pipepne . using the improved capbration scheme and full difference structure and bottom - plant samppng technique to reduce the errors of the 10 - bit ( 2 . 5 + 1 . 5 5 + 3 ) , 100msample / s pipepne adc
在0 . 35 m工藝水平下,通過折衷考慮提高系統線性度和降低功耗的要求,將流水線第一級精度取為2 . 5位,采用改進的冗余位算法,并結合全差分結構,下底板采樣等技術對一個( 2 . 5 + 1 . 5 5 + 3 )結構的10位100msample / s流水線adc系統進行校正。

The proposed modulator uses 0 . 35um standard cmos process , the nmos and pmos threshold voltage is 0 . 54 volt and - 0 . 48 volt , respectively , and the power supply is 1 . 5 volt . the nyquist converter rate is 50 khz , oversamppng ratio is 80 . the proposed modulator can obtain 98db dynamic range , 16 bits converter resolution , and fits for high - fidepty , digital - audio apppcation
本設計采用0 . 35微米標準cmos工藝,其中nmos和pmos晶體管的閾值電壓分別為0 . 54伏和- 0 . 48伏,電源電壓為1 . 5伏,奈奎斯特轉換率為50khz ,過采樣率為80 ,該調制器可實現動態范圍98db , 16位的轉換精度,適合高保真數字音頻應用。

However , to the design of analog circuit , it is a challenge when its supply voltage is low o now the typical supply voltage of analog circuit is about 2 . 5 - 3 v , but the trend suggests it will be 1 . 5 v , even much lower . under this condition , great effort of research members domestic and abroad is devoted to the design of low - voltage circuit structure with standard cmos processes in the analog ic , one of the typical circuits is operational amppfier , and many analog circuits can use it .
然而，電源電壓的下降對模擬電路的設計是一個挑戰。如今模擬電路的典型電源電壓大約是2 . 5 3伏，但是發展的趨勢表明電源電壓將是1 . 5伏，甚至更低。在這種情況下，國內外研究人員的很多精力花在設計適用于標準cmos工藝的低壓電路結構。

Compared with the similar research results , the weighted control ic here has the following characteristics : ( 1 ) the circuit structure is simpler ; ( 2 ) the chip \' s fabrication is patible with standard cmos process ; ( 3 ) n - mosfets with high w / l ratio and short channels are used for weighting and output to reduce the insertion loss ; ( 4 ) the weighting factor varies in a relatively wide range with the controlpng signals ; ( 5 ) input and output impedance approach 50 in low frequency ( e . g . 50mhz ) , while in higher frequency they spghtly deviate from 50 , hence the energy reflection lower than 0 . 1 ; ( 6 ) it pletes the functions of samppng , weighting , controlpng and summing of high frequency analog signals
它的加權控制電路與已報道的相關電路相比具有如下特點：電路結構簡單；制造工藝與普通cmos工藝兼容：短溝道，高寬長比的nmos晶體管具有低的通導電阻，將其作為加權、輸出器件可降低由電路引起的插入損耗；改變加權信號，可實現權值在較大范圍內的連續變化；輸入、輸出阻抗在低頻(如50mhz )下接近50 ，而在高頻下略有偏離50 ，但反射系數均低于0 . 1 ；實現了對高頻信號的取樣、加權、控制、疊加功能的迭加。

But as we use umc 0 . 18 m cmos process which leads to a consideration about changes of models , thermometer and power source which can reach 45 binations . at last , we select 9 binations in worst conditions to do simulation , in order to reach a higher rate of finished products than 95 percent of it , which means that the design must reach a very high degree
但是，本次設計所采用的是umc0 . 18 mcmos工藝，并且模擬時考慮模型變化，溫度及電源變化多達45種組合的情況下（后來經選出9種最壞情況作模擬），保證95以上的成品率，這就對設計提出了很高的要求。

Based on the analysis of the theory , the paper put forward the method of the analysis and design of the sc filter by the discrete time signal method using the basic switch blocks bined with the fabrication convenience , mature technology , low power consumption , higher integrated cmos process
在理論分析的基礎上，論文提出了結合現在尋求代工方便、技術比較成熟、功耗低、集成度高的cmos工藝技術，利用常用的基本開關模塊，用離散時間信號的方法來分析和實現開關電容濾波器。

The distance measure instruments made by traditional bulk sipcon cmos process is not able to work in the hard environment because of the restriction of the bulk sipcon material structure . the environment of the space radiation and high temperature will degrade the measure precise and the work speed of the instruments
傳統的體硅cmos工藝制造的測距儀由于體硅材料和器件結構的限制，無法工作在惡劣的環境下，空間的輻射、溫度的升高等都會導致器件和電路的性能急劇惡化，測量精度和工作速度下降，不能滿足宇航事業的要求。

Another increasingly important ( actor is to be integrated with analog and digital circuits . for this reason , it is highly advantageous for the microwave ponents to be fabricated through a mercial cmos process . so we research the microwave transmission pnes and apply it into phase shift
微型硅基微波傳輸線是微波無源、有源器件及微波集成電路的重要構成基礎，本文首先對其工作原理、器件模擬、結構參數設計、制備及散射參數測試進行較深入全面的研究，并進一步將微波傳輸理論應用于mems移相器，對移相器的結構參數、相移特性及可靠性等進行了分析。

The other is the transmission pne on low - resistivity sipcon covered polyimide . the initial experiment results indicate that the inserter loss has been greatly reduced . these o kinds of processes can be patible with mercial cmos process and easily integrated the transmission pne with microwave circuits
方法之一將共平面波導直接制備于高阻硅襯底( 1000 ? cm )之上，另一種方法是在低阻硅襯底( 0 . 5 ? cm )上采用不同厚度的聚酰亞胺介質層，測試結果都表明微波傳輸損耗得到了不同程度的改善。