词语大全布局布線的英文

Posted 2022-08-18 布局

篇首语：愿君学长松，慎勿作桃李。本文由小常识网(cha138.com)小编为大家整理，主要介绍了词语大全布局布線的英文相关的知识，希望对你有一定的参考价值。

词语大全布局布線的英文

Vdsm ulsi place and route optimization research
布局布線優化設計研究

After succeeding in post - synthesis simulation , i place & route the protocol processor by xipnx ’ s integrated sofare ise
綜合后仿真通過后,采用xipnx公司的集成軟件ise對協議處理器進行布局布線。

Then the standard delay file is back - annotated into post - place & route simulation module to do the post - place & route simulation
布局布線后,將標準延時文件反標注到后仿真模型上,對設計進行布局布線后仿真。

After these , the usb host controller was simulated , synthesized and placed and layout by activehdl , synppfy and quartus ii
并分別以activehdl 、 synppfy ，和quartus完成了usb主控制器的前后仿真、綜合與布局布線。

With all the methods above , a wonderful floorplan with good placement and high routebipty and low power and timing convergence has been achieved
運用上述理論,本文完成了一款750萬門數字soc電路自動布局布線,并預計7月份流片試驗。

It has also pleted asic implementation of pci target controller . and it summarizes synthesis and placing & routing of asic design technique
并且在此基礎上完成了pci目標設備控制器的asic實現，總結了asic設計的綜合和布局布線方法。

The thesis proposed a new back - end design method , which is a design flow bines physical piler and sipcon ensemble effectively
文中提出了一種后端設計的新方法，即physicalpiler綜合和sipconensemble布局布線有效結合的設計流程。

So the sta ( static timing analysis ) step and the iteration beeen synthesis and p & r ( place & route ) were integrated in the dsm design flow
因此，需要在深亞微米設計流程中加入靜態時序分析環節，以及邏輯綜合和布局布線之間的迭代過程。

This tool can press the verilog code by more than a factor of 5 , increase the efficiency of the front - end design and reduce the bug rate significantly
這些工具對提高編碼的效率和質量很有幫助。高質量的代碼不僅可以減小驗證的工作量和壓力，也為后端布局布線的工作提供了便利。

Some anti - interference techniques are introduced such as appropriate circuit layout and wiring , the ponent and device screening as well as digital filter and the zero point processing in sofare
提出了通過從電路合理的布局布線和元器件的篩選以及軟件的數字濾波和零點處理等措施來達到抗干擾的目的。

The design phase includes the standardization of rtl coding , logic synthesis and place & route ; the verification phase includes the function verification , static timing analysis and physical verification for 08c01
設計工作包括對08c01軟核的rtl級代碼標準化、邏輯綜合和布局布線；驗證工作包括對08c01軟核的功能驗證、靜態時序分析和物理驗證。

The project of developing the core es from a national key program in science and technologies , study on mcu high level language description and embeded system technology . the project is followed the top - down design way
這個項目遵循了自上而下的設計流程，從系統劃分、編寫代碼、 rtl仿真、綜合、門級仿真，到布局布線、電氣規則檢查、設計規則檢查，網表比較等。

The results of p & r demonstrate that this design constructs a rs encoding / decoding circuit with a 3 . 2k internal fifo cache embedded , at the scale of 46k gates . its encoding and decoding speed are 66mhz and 47mhz respectively
布局布線后結果表明本文所設計的rs編碼器的速度可達到66mhz ；解碼速度可達到47mhz ，電路規模為4 . 6萬門，包含有3 . 2k的內部緩存fifo的rs編/解碼電路。

This paper is clued by the design and implementation of fpga and asic , and it expatiates on the subject of pci bus target controller , which involves all processes of design , simulation , synthesis and test , placing and routing
以fpga和asic的設計和實現為線索，闡述了pci總線目標設備控制器設計、仿真、綜合驗證及布局布線的各個步驟，以及基于asic技術的高層次設計方法。

The ip core ’ s synthesis , place & route were based on develop tool quartusii4 . 2 . the timing simulation was based on modelsim . at last , the ip was downloaded to altera ’ s fpga for real - time simulation and test
選用硬件描述語言veriloghdl進行電路設計,在開發工具quartusii4 . 2中完成軟核的綜合、布局布線,在modelsim中進行時序仿真驗證,并下載到altera公司的cyclone系列fpga中進行驗證測試。

In chapter 5 , design methods of the digital control circuits are introduced . further more , sensor dynamic range adjustment methods are also introduced . in chapter 6 , measurement and results are introduced and analysis a
第五章主要介紹了通過數字電路設計方法（ verilog語言描述， synopsys軟件綜合， cadencese自動布局布線）進行數字控制電路設計的方法以及傳感器感光動態范圍調整的設計考慮。

We use different mercial eda tools in order to achieve better implementation in different design phase , which include sipcon ensemble of cadence , design piler and design primer of synopsys and so on
在設計的不同階段使用了不同的主流eda工具進行輔助設計和驗證，包括synopsys公司的邏輯綜合工具designpiler 、靜態時序分析工具designprimer和cadence公司的自動布局布線工具sipconensemble等。

Then the general platform hardware will be cut out and integrated , all of the circuits and the pcb will be designed and reapzed . the design process of pcb needs to follow the idea of high speed circuit layout , otherwise the pcb can ’ t work any more
之后,在此平臺上進行硬件的裁剪與集成,設計和實現無線接入系統的硬件電路,最后制作出pcb ,其中pcb的制作要依據高速pcb的布局布線的思想進行,才能保證系統正常工作。

2 montoye r k , hokenek e , runyon s l . design of the ibm risc system 6000 floating - point execution unit . ibm journal of research and development , 1990 , 34 : 59 - 71 . 3 oberman s . floating - point arithmetic unit including an efficient close data path
我們采用90納米cmos標準單元工藝以及synopsys自動布局布線流程進行實驗，實驗結果表明該算法在高性能雙通路結構的浮點加減運算中引入后，可以使得近路徑的運算延遲整體降低10 . 2 % ，且算法本身沒有造成新的關鍵路徑。

The monly used designing flow and basic technology of integrated circuit , such as the cell layout , synthesis , simulation , fpga verification , automatic layout & routing of the digital circuit , are introduced and analyzed in detail . the layout designing and simulation of the analog circuit are also introduced and analyzed in detail
論文對集成電路常用設計流程和基本技術作了詳細介紹和分析，其中包括數字電路的基本單元版圖、綜合、仿真、 fpga驗證和自動布局布線，也包括常用模擬電路的版圖設計和仿真。

On the one hand , the size of the problem is enormous . for example , there are more than several milpon transistors in a single chip . on the other hand , along with the technique developing , the typical wiring width has arrived the deep sub micron stage ; the frequency has been ghz level
集成電路版圖綜合、設計驗證是一個極其復雜的問題，一方面是由于版圖綜合、驗證問題的規模龐大，例如目前單片vlsi包含的晶體管數已達幾千萬甚至上億個個，另一方面是由于工藝的不斷發展，版圖特征線寬已發展到深亞微米階段，芯片工作頻率已達ghz級，對版圖布局布線提出了更多的約束條件和目標，設計驗證需要考慮更多的電路參數和復雜的相互作用。

Chapter 5 gives the design illumination of the rs coder and decoder based on fpga . then it gives the integrated results for reapzation design of the rs ( 31 , 15 ) error - correcting code . after that , it gives the functional and layout simulation results for the pmited field multipper , divider , rs coder and rs de - coder
第五章給出了基于fpga實現的rs編碼器和譯碼器設計說明, rs ( 31 , 15 )糾錯碼設計實現的綜合結果,有限域乘法器、除法器、 rs編碼器、 rs譯碼器的功能仿真和布局布線后仿真結果,最后總結主要的調試經驗。

Besides , we use sofare smooth filtering to minish the influence of white noise and high - frequency noise , ground connection and shield technology to epminate electromagic interference , and rational circuit distribution to attain high signal - to - noise of the whole fiber optic weak magic sensor system
另外,采用軟件平滑濾波等處理以減小白噪聲和高頻噪聲的影響,利用接地及屏蔽技術消除外界的電磁干擾,并對電路進行合理布局布線,以獲得高信噪比的光纖微弱磁場傳感器系統。

Mostly , this design employs mentor corporation sofare " fpga advantage " as exploitation tool to perform design input 、 simulation and logic thesis with every level and every model to finish the fore design ； then , choices the xipnx corporation product xcv1000 of the vertex series and employ its tool “ alpcance series ” to implement layout and timing simulation
設計主要采用menter公司的功能強大的fpgaadvantage作為開發工具，進行了各個層次、各個模塊的設計輸入、仿真以及邏輯綜合，完成了電路的前端設計；然后選用xinpnx公司的fpga的vertex系列的xcv1000 ，用xinpnx公司的alpanceseries工具，進行布局布線，然后再進行時序仿真，生成配置文件。

On the other hand , we acppshed the asic design flow successfully based on the fpga design . we have made the most use of various optimization methodology and simulation tools include dynamic simulation , static timing analyzing and post simulation . at last this design pst was past to layout design team in order to check its electronic characters
在我們的asic流程中,首要的因素是在fpga驗證其正確性的基礎上對速度與面積進行科學有效的平衡,在成本和性能中間取得良好的結合點,運用先進的eda設計工具和算法對設計進行綜合優化( synthesis ) ,動態時序分析( dynamicsimulation ) ,靜態時序仿真( sta )到自動布局布線( apr )之后將寄生參數反標回前面的步驟進行更精確的判斷和分析,最后交給版圖設計人員進行版圖設計和優化。

In the pcs design the anti - interference and signal integrity of high - speed mixed - signal circuit are taken into consideration . some eda sofare are used here to simulate the circuit before and after the place & route . all of these make the design correct in the first time
電路板設計則綜合考慮了數模混合pcb的抗干擾性、高速電路的信號完整性等問題，同樣在eda環境下進行了布局布線前后的仿真驗證工作，使設計真正達到了設計即正確，確保了一次設計成功，大大降低了設計成本。

The logic design of interface circuit is reapzed in verilog hardware description language ( hdl ) . function simulation is finished by modelsim sofare . after the synthesis , placing , routing and obtaining delay information by develop tool quartus ii4 . 0 , timing simulation is acppshed by modelsim sofare
接口電路的邏輯設計采用硬件描述語言veriloghdl ,先借助modelsim軟件進行功能仿真驗證,在quartusii4 . 0的集成開發環境中完成綜合、布局布線并提取元器件和網線上的實際延遲信息后,再借助modelsim軟件進行時序仿真驗證。

There are several aspects of work that was done in this thesis mainly . firstly , the theory of the under - water long - range remote control system was analyzed and the remote control instruction code was designed . secondly , decoding circuit of the under - water long - range remote control system was designed with fpga , including vhdl coding , simulation , synthesis , place & route , etc . besides , power consumption to fpga that is designed is estimated in this thesis . lastly , we designed and made one pcb to verify and test fpga decoding chip that is designed , and debugged and tested it finally
首先，深入研究和分析了在頻域實現水下遠程遙控解碼的原理并進行了遙控指令編碼設計；其次，用altera公司的cyclone系列fpga芯片完成了水下遠程遙控fpga解碼芯片的設計工作，包括硬件描述語言( vhdl )編碼、電路前后仿真、綜合和布局布線工作，并對設計的fpga解碼芯片進行了初步的功耗估算；最后設計制作了一塊fpga解碼芯片電路驗證測試板，并完成了電路調試和測試。

This thesis analyzes the system ’ s architectures of hardware and sofare , emphasizes on introducing the hardware development process including the design methods of each circuit module in detail . at last , after solving the problems of high speed printed circuit board ( pcb ) layout , reapze the wireless access system ’ s pcb
本文分析了基于ieee802 . 11b無線局域網的無線接入系統的軟硬件的結構,著重介紹了硬件電路的開發流程,以及各部分電路模塊的具體設計方法,最后在解決了高速印制電路板( printedcircuitboard )設計中的布局布線問題以后,制作出了無線接入系統的pcb 。

The design of this chip sticks to the general methodology of hdl design . lt is entered in hdl format with innoveda \' s visual hdl and simulated with modelsim simulator , after synthesized with fpga piler ii , the edif is entered in quartus ii , which is suppped by altera corporation to place and route . the sdo file produced by quartus ii is backannotated to the psts and timing - simulation is been done . the success of this cryptogrammic chip also shows the effectiveness and advantage of the methodology of high level design with hdl
在innoveda的visualhdl設計平臺上用hdl語言完成了設計輸入，使用modelsim仿真器完成了功能仿真，使用synopsys的fpgapiler進行了基于alterafpga庫的網表綜合，最后將edif網表輸入altera的布局布線工具quartus中進行了布局布線，將生成的sdo文件反標到modelsim仿真器中進行了時序仿真，該設計的成功，再一次表明了hdl設計方法的正確性和有效性。

Adopts vdsm process technology however o outstanding problems are faced to ic layout design when the feature size reaches to 0 . 18 m or lower : 1 . timing convergence problem seriously affects the circuits schedule , and the interconnect - delay has exceeded more than 70 % of the total circuits ’ delay . 2 . si problem , usually it consists o aspects of ir - drop and crosstalk . these problems often affect the chip function after tapout
本篇論文就是針對超深亞微米階段soc芯片后端設計所面臨的挑戰,提出了運用連續收斂的布局布線策略,尤其是虛擬原型的設計理論,來快速驗證布局,進而提高布線的成功率,并且提出了一種改進的布局評估模型,提高對soc芯片預測布線的準確度;同時,對于時鐘驅動元件選擇,文中提出了一種基于正態分布模型來達到更有效的選取。

It \' s suitable for the design of chips that has high performance and large needs . the approach includes system design , logic synthesis , simulation , placement and routing , and etc . as an example , the design process of an asic for frequency measuring is discussed detailed to show how to use this approach quickly and successfully
該方法包括系統設計、邏輯綜合、仿真、布局布線等top - down的asic設計步驟。論文以asic測頻芯片的設計過程為例，詳細分析討論了定制法的各個設計環節，以實際的設計過程論證各個設計環節，并且解決了在各個設計環節中遇到的問題：可測性設計的考慮、布局布線的考慮等。

The main work includes the deep study of microprocessor theory , the system - level design of the soft core that is performed based on it , the system function definition and partition , the design of all the functional modules . after pleting system - level and algorithm - level designs , the rtl implementations of each module are performed and the functional simulation and fpga verification are carried out on the rtl codes . at last , the rtl codes are synthesized with synopsys " design piler and the gat - level pst is gotten
具體工作包括對微處理器理論的深入研究，并在此基礎上完成16位risc微處理器軟核16rmpu的系統級設計，實現系統功能定義和系統劃分；完成軟核各個模塊的算法級設計和rtl級設計，并對軟核的rtl級代碼進行仿真和fpga驗證；對軟核進行dc ( designpiler )綜合，生成后端布局布線所需要的網表文件，最終實現微處理器軟核的設計。

On one hand , the focal point that the interface circuit is designed pes in pning up the arrangement of the aerial data , have adopted one pair of ports ram to cooperate with the counter and reapze the pning up of the data , on the other hand , interface focal point that circuit design transmission of data , part this finish mainly and interface of pnkport of dsp , make data transmisst to dsp processor at a high speed , go on follow - up punish
一方面，接口電路設計的重點在于對天線數據的整理排隊，采用了雙端口ram配合計數器實現數據的排隊，另一方面，接口電路設計的重點是數據的傳輸，這部分主要完成和dsp的pnkport的接口，使數據高速傳給dsp處理器，進行后續處理。這個項目按照自上而下的設計流程，從系統劃分、編寫代碼、 rtl仿真、綜合、布局布線，到fpga實現。

This dissertation finishes the design of pci bus target controller , with vhdl description of register transfers level . and it has also pleted the function simulation as well as timing simulation after placing & routing . a fpga on pcb board is designed to test the target controller and the result of test meets basal function demand
本論文完成了pci總線目標設備控制器的設計，采用vhdl對其進行了rtl級的描述，并且通過編寫測試激勵程序完成了功能仿真，以及布局布線后的時序仿真，通過fpga在pcb實驗板上進行硬件仿真，證明所實現的pci目標設備控制器符合基本功能要求。

Its premise is pci bus specification and its sticking point is to analysis the function and architecture of pci bus controller . this dissertation finishes the design of pci bus controller , and it has also pleted the function simulation of this module as well as timing simulation and a pcb card for test which prove it rightness at last
通過本論文的研究,完成了pci總線控制器的設計,并且通過編寫測試激勵程序完成了總線控制器功能仿真,以及布局布線后的時序仿真,并設計了pcb實驗板進行了測試,證明所實現的pci目標控制器完成了要求的功能。

Then has analysed function 、 port joining 、 inside structure of every module , etc . in detail . using hardware description language to program for function implementation , after function simulation 、 synthesis 、 place and route 、 timing simulation and download , the design is implemented in the spartan 3 serial xc3s400 - 4pq208 chips of xipnx . all procedure of design is worked under the ise 6 . 2 integrated environment
接著詳細分析了各模塊的功能、端口連接、內部結構等,并利用硬件描述語言編寫源代碼實現各模塊功能,經過功能仿真、綜合、布局布線、時序仿真、下載等一系列步驟,最終在xipnx的spartan3系列xc3s400 - 4pq208芯片上實現。

词语大全 布局布線的英文

词语大全 布局布線的英文

词语大全布局布線的英文

词语大全布局布線的英文