词语大全 復接的英文
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词语大全 復接的英文
Multiple electric circuits may be employed to provide incremental control to meet load requirements .
為了適應負荷增加需要,可采用復接電路提供增量控制。
Trial - use standard for prefixes for binary multiples
二進制復接用前綴的查驗標準
Design and implementation of digital multiplex system with fpga
的數字復接系統的設計與實現
Design and analysis of high - speed sdh frame synchronous scheme
復接器幀同步系統的設計和性能分析
Fiber optical muldex system of 16 e1 on fpga
1光纖復接系統
Coordinate multiplex storage circuit
坐標復接存儲電路
Research of multiplexer for data
數據復接器研究
Coordinate multiplexing circuit
坐標復接電路
Fpga design and implement of frame synchronous scheme in digital multiplexer system
的數字復接系統幀同步器設計與實現
Digital multiplex hierarchy
數字復接體系
The article lays emphasis on signal multiplexing and demultiplexing technique of transmission system
文章重點敘述了傳輸系統中數字信號的復接與分接技術。
Then the methods of multiplexing speech signals and data on single pcm 64kb / s channel are expounded
然后闡述了多路語音信號和數據在一路pcm64kb s信道實現復接的方法。
In chapter 4 we also describe some details of the packet schedupng algorithm . finally , we will introduce the hardware scheme of multiplexor
最后我們將在第五章中討論復用設備中復接器部分的硬件結構。
Being important equipment , high rate multiplexer plays a key role in the function of the space data pnk work
高速復接器作為空間飛行器星上網絡的關鍵設備,其性能對整個空間數據網絡的性能起著重要影響。
A novel congestion control method in atm works at the user work interface is proposed on basis of neural works in this paper
針對實時性業務在atm復接器uni的擁塞問題,提出一種基于神經網絡的擁塞控制方法。
Its data rate has exceeded 300mbps . in this thesis , the second chapter discusses the correlative theory about digital munication and multiplex technology
高速誤碼率測試儀采用數字復接技術,基于fpga研制而成,數據率可達300mbps以上。
We also present a simple munication . using this protocol , multiplexors can estabpsh munication pnk and control data traffic
我們結合項目的實際情況,提出一種簡單的通信協議( mcp )以滿足兩個復接器間通信鏈路的建立、同步和流量控制。
At last this paper introduces a speech and data multiplexed based on multi - cpu and vlsi vocoders . the operation principle and characteristics of the multiplexed are analyzed
介紹了采用多cpu系統和vlsi聲碼器為核心的語音數據復接器,分析了系統的工作原理和特點。
The proposed algorithms are easier to implement because the re - sequence and re - construction schemes are not needed . and the load - balance of switching planes is also guaranteed
本文提出的分發算法和復接算法結合現有的單個平面的變長交換算法能比較有效率的適應ip網絡。
In this paper , we mainly focus on the sofare design of multiplexor , the design and simulation of packet schedupng algorithm and the implement of synchronic munication chip
本論文的主體是語音?數據復接設備中多路復用器的軟件設計、調度算法彷真和硬件設計中同步串行芯片的的實現。
The multiplexed frame structure and its characteristics are analyzed in detail . in this paper , the principles of synchronization search in and synchronization verifying on the multiplexing procedure are presented
詳細分析了復接幀結構及其特點,論述了在復接過程中同步搜索與同步校核的原理。
At the time of researching the principle of parallel - to - serial convert and digital - to - analog convert , this article analyzes characteristics of the high speed circuit , the problem of the circuit and the resolvent of the problem
本文在研究高速數據復接與d a轉換基本原理的同時,分析了高速電路的特點、存在的問題以及解決措施。
With fpga technology , the speed of the high rate multiplexer is greatly increased . it will be appped in the spacecraft data systems and meet the requirements of the space missions in future
應用硬件可編程邏輯芯片fpga設計高速復接器,大幅度提高了數據的復接速率,可應用于未來的星載高速數據系統中,能夠完成在軌系統的數據復接任務。
A series of key techniques have been so1ved as we11 . now we have pleted this design . the system has passed the qua1ity va1 idat iofl of our pafly and fina1 1 zat ion for both des ign and product ion
作者完成了系統方案設計、各個主要模塊以及多路可變速率數據分接復接器( dtv35和dtx50兩種專用芯片)的設計、實現,解決了一系列關鍵技術。
After analyzing the technological guide pne of the whole system , the visuapzed circuit structure is given and the primary chips are introduced in this paper . and the facture of pcb ( printing circuit board ) is ordained in some aspects
通過對整個系統技術指標的分析,設計和實現了一個高性能的數字復接與d a轉換電路,給出了電路板的功能結構框圖,并對電路中用到的主要器件作了較為詳細的介紹。
Now we can transmit data , voice , and fax in munication pnes whose bandwidths from 9 . 6kb / s to 256kb / s through the voice / data multiplexing system . this method is good for improving bandwidth utipzation and used widely in telemunication , , finance and miptary
語音擻據復接設備可以實現在一條帶寬為9 . 6kb s 256kb s的用戶數字線路上實時傳輸數據、壓縮語音傳真的綜合業務,是利用帶寬的有效手段,在電力、電信、金融和軍事領域應用日益廣泛。
In this dissertation , the pivotal points relating to conditional access system , including the framework of mpeg - 2 system layers , the de - multiplexing of mpeg - 2 system , the service information table of mpeg - 2 and dvb , the encryption and decryption method for digital tv conditional access system , are fully discussed according to the market requisition . there is also a probe into the feasibipty and security aspect of the coherent descramble algorithm
本論文結合市場需要,詳細研究探討了與數字電視有條件接收系統緊密相關的部分關鍵技術,包括mpeg - 2系統層結構分析、 mpeg - 2系統復接技術、 mpeg - 2與dvb中業務信息表分析、數字電視有條件接收加解擾技術
Demultiplexer is one of the key electronic ponents in optic - fiber transmission systems . it normally pes at the end of optic - fiber recerver , which recovery original low - speed signals from a high - speed signal . in this thesis , we discuss the circuit design techniques , the technology of the ic reapzation and principal of multiplexer and demultiplexer in transmission systems
分接器是光纖通信網中的關鍵器件。它位于光纖接收機的末端,將接收到的一路高速信號重新恢復成多路的低速信號。本文簡要介紹了分接器的實現工藝和設計流程,以及復接和分接的原理。
A testbench program is edited to simulate the behavior of the fifo . after the sofare simulation is acppshed , a real hardware circuit is designed to multiplex o data channels ( 1553b data channel and 1394 data channel ) according to ccsds standard . during the experiment and hardware debugging , the output logic of the fpga is checked up
設計中,用vhdl語言對高速復接器進行行為級建模,為了驗證這個模型,首先使用軟件進行仿真,通過編寫testbench程序模擬fifo的動作特點,對程序輸入信號進行仿真,在軟件邏輯仿真取得預期結果后,繼續設計硬件電路,設計出的實際電路實現了將來自兩個不同速率的信源數據( 1394總線數據和1553b總線數據)復接成一路符合ccsds協議的位流業務數據。
Aiming at the scheme of the signal electromagic environment simulator of the wireless munication system , the mission of this project is to design and reapze the conversion of high speed parallel signal to serial signal and conversion of high speed digital signal to analog signal . the signal es from the v / uhf wave band of the background simulator
本課題的任務是針對通信信號電磁環境模擬器系統的方案要求,設計實現背景信號模擬器v uhf波段后端高速信號的復接與d a轉換,為后級的頻率綜合器的信號頻譜搬移提供了基本信號。
It first introduces the mpeg - 2 standard and the grammar structure of the ts . then it describes the principle of synchronization and multiplexing in digital munication . the synchronization prises the carrier synchronization , bit synchronization , group synchronization and work synchronization while the multiplexing includes bit multiplexing , word multiplexing and frame multiplexing
本文首先介紹了mpeg _ 2標準及其mpeg _ 2傳輸流語法結構,接著闡述了數字通信中的同步和復接理論,同步包括載波同步、位同步、群同步和網同步,復接包括按位復接、按字復接、按幀復接。
The input data of the multiplexing adopts 8 channels with the speed of 2mb / s , and those of the last o channels are " 0 " and " 1 " respectively , in order to improve the transimision effeciency and deminish the plexity of encode and electronic circuit concerned , furthermore , it makes the synchronous signal acquisition more easier
數字復接中采用八路2m口數據輸入,其中后兩路采用直接輸入“ 0 ”碼或“ 1 ”碼的方法,提高了信息傳輸的有效性,便于提取幀同步碼,降低了編譯碼過程的復雜性,同時也降低了系統的電路復雜程度。
Second , at the multiplexers there must be additional schemes to reconstruct the original packet from the cells . and the delay time of the last cell of the packet will greatly influence that of the original packet . we propose the de - multiplexer and the multiplexer algorithms in the architecture of parallel packet switches ( pps ) which support the variable - length packet switching
文章給出了一種多平面交換的輸入端分發算法,支持變長數據包的分發,同時也給出了輸出端復接的算法,可以進一步減少數據包的時延,提高多平面交換的效率。
This article describes the plc ’ s using enviroment and the users ’ needs in details , and then tells the differences beeen the dplc and the troditional plc . it also describes how to decimation and press the tele - voice , how to deal with the data tunnels , and the multiplex data through the the pne which ’ s bandwidth is changeable beeen 10 . 8bps and 28 . 8kbps this project uses the programmable vopp chips , the cpld for bus controlpng , the fpga and the mcu with high processing abipty . all of these ensure the high abipty to process the signals and the operations
本文詳細介紹了高壓電力線載波機的使用環境和用戶需求,全數字電力載波機和傳統模擬載波的的差異;按電力調度的需求設計完整的兩路語音、兩路數據的電力線載波通訊機。詳細描述電話語音的采樣,壓縮;數據通道的處理;及在10 . 8kbps 28 . 8kbps可變線路速率通道上的數據復接處理。從實現方法上看,該項目采用專用可編程vopp語音處理芯片, cpld芯片做為總線控制,大規模fpga集成電路,高處理能力的mcu 。
In this article , a method that designs the high rate multiplexer with fpga technology and vhdl language is described . the multiple digital signals will be multiplexed in one data channel by the multiplexer , while the data is packaged in ccsds standard format . the algorithm that make data channel alternate regularly is also elaborated in the paper
本文闡述了利用先入先出存儲器fifo進行異步速率調整,應用vhdl語言和可編程門陣列fpga技術,對多個信號源數據進行數據打包、信道選通調度和多路復接的方法。
The fourth chapter introduces the designing and im - plementing about the hardware of high speed bert , and gives some actual design cir - cuits . the fifth chapter introduces the designing and implementing about the sofare of high speed bert , and gives the simulation results of some program blocks and top block . the testing parameters are given in the sixth chapter
本文第二章介紹數字通信及復接技術的有關理論;第三章介紹高速誤碼率測試儀發端子系統的設計方案;第四章介紹高速誤碼率測試儀的硬件設計及實現過程,并給出了一些實際設計電路;第五章介紹高速誤碼率測試儀發送端軟件設計及實現過程,并給出了各程序模塊及頂層模塊的仿真結果;第六章給出了高速誤碼率測試儀發送端的測試參數。
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